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Overview

Project website spinalhdl.github.io/SpinalDoc-RTD
Instructions for translators

SpinalHDL的使用说明
Project maintainers User avatar Readon User avatar SpinalHDL-CN User avatar tsy0123
Translation license Creative Commons Zero v1.0 Universal
Translation process
  • Translations can be made directly.
  • Translation suggestions can be made.
  • Translations are reviewed by dedicated reviewers.
  • Any authenticated user can contribute.
  • The translation uses bilingual files.
Source code repository git@github.com:SpinalHDL-CN/SpinalDoc-RTD.git
Repository branch master
Last remote commit update .pot files 0dd5fe26e
GiHub Action Bot authored 2 weeks ago
Last commit in Weblate Translated using Weblate (Chinese (Simplified)) cb52ddbca
User avatar tsy0123 authored 4 months ago
Weblate repository https://hosted.weblate.org/git/spinaldoc-rtd/index/
File mask source/locale/*/LC_MESSAGES/SpinalHDL/Legacy/pinsec/hardware_toplevel.po
Translation file Download source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot
Last change None
Last author None
8 days ago

String statistics

Strings percent Hosted strings Words percent Hosted words Characters percent Hosted characters
Total 83 708 4,368
Approved 0% 0 0% 0 0% 0
Waiting for review 0% 0 0% 0 0% 0
Translated 100% 83 100% 708 100% 4,368
Needs editing 0% 0 0% 0 0% 0
Read-only 100% 83 100% 708 100% 4,368
Failing checks 0% 0 0% 0 0% 0
Strings with suggestions 0% 0 0% 0 0% 0
Untranslated strings 0% 0 0% 0 0% 0
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User avatar None

Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
The “source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot” file was changed. 5 months ago
User avatar None

Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
The “source/locale/gettext/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot” file was changed. 5 months ago
User avatar None

Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
File “source/locale/template/SpinalHDL/Legacy/pinsec/hardware_toplevel.pot” was added. 6 months ago
User avatar None

String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
And finally some connections between components are required like interrupts and core debug module resets
And finally some connections between components are required like interrupts and core debug module resets
6 months ago
User avatar None

String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
To connect all toplevel IO to components, the following code is required :
To connect all toplevel IO to components, the following code is required :
6 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
Misc
Misc
6 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
The interconnection between the APB3 bridge and all peripherals is done via an APB3Decoder :
The interconnection between the APB3 bridge and all peripherals is done via an APB3Decoder :
6 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
Some documentation could be find :ref:`there <stream>`. In short, it's just some pipelining and interconnection stuff.
Some documentation could be find :ref:`there <stream>`. In short, it's just some pipelining and interconnection stuff.
6 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
``halfPipe`` / >> / << / >/-> in the following code are provided by the Stream bus library.
``halfPipe`` / >> / << / >/-> in the following code are provided by the Stream bus library.
6 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Legacy/pinsec/hardware_toplevel
  3. English
Then to reduce combinatorial path length and have a good design FMax, you can ask the factory to insert pipelining stages between itself a given master or slave :
Then to reduce combinatorial path length and have a good design FMax, you can ask the factory to insert pipelining stages between itself a given master or slave :
6 months ago
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